Senior Staff verification Engineer – Mixed-Signal Simulation (SystemC/SystemVerilog)

Job Summary:
We are seeking a highly experienced Senior Staff Verification Engineer to architect mixed SystemC and SystemVerilog/UVM verification environment for out next generation SOC. The ideal candidate will have deep expertise in digital system co-simulation, behavioral modeling, and verification methodologies for complex SoCs and IP blocks.

Key Responsibilities

• Lead the development of SystemC/TLM models for SoC components including CPUs, memory subsystems, interconnects, and peripherals. 
• Collaborate with architecture, design, and verification teams to define modeling requirements and ensure alignment with system-level goals. 
• Drive performance modeling and simulation to evaluate architectural trade-offs and optimize system behavior. 
• Integrate SystemC models into virtual platforms for pre-silicon software development and validation. 
• Mentor junior engineers and contribute to best practices in modeling methodology and infrastructure. 
• Support model integration with other simulation environments (e.g., QEMU, SystemVerilog, Python-based frameworks). 
• SystemC and SystemVerilog mixed simulation. Experience with DPI and/or UVM connect is a plus. 
• Document modeling architecture, APIs, and usage guidelines.