Senior Yield Enhancement Engineer

The Role: Senior Yield Enhancement Engineer 

We are seeking a highly experienced Senior VLSI Product and Test Engineer with 7+ years of relevant experience in Semiconductor Testing/Failure Analysis/Yield Enhancement. The successful candidate will look at ATE datalogs, understand the defects in detail, disposition wafers based on ATE data and drive FA/Yield enhancement using physical/optical inspection techniques used in FA. 

Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing. 

Key Responsibilities  

• Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns. 

• Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques specific to Cerebras hardware. 

• Develop and execute FIB (Focused Ion Beam) edit plans for Silicon root cause validation. 

• Communicating with OSATs and Fab to drive production testing in HVM environment. 

• Understand DFT strategies including hierarchical scan chains, distributed BIST, SRAM test methodologies, and perform diagnosis on ATE data. 

• Collaborate closely with DFT engineers, silicon architects, designers, performance teams, and software engineers to enhance overall testability and yield 

• Refine test programs across di/dt behavior, voltage-frequency characterization space, current limits, and thermal constraints based on ATE logs and disposition learnings. 

• Understand and write Python scripts and UNIX environment. 

Required Skills & Qualifications 

• Bachelor's or Master's degree in Electrical Engineering / Computer Engineering, or related field 

• 7+ years of hands-on experience in semiconductor test engineering/ FA/ Yield Enhancement. 

• Hands-on experience with lab debug tools including Oscilloscopes (high-speed probing and signal integrity), wafer probe stations, probe cards, Keyence/Optical inspection systems, and advanced imaging techniques. 

• Failure analysis (FA) expertise including use of optical probing tools, physical inspection workflows, and correlation of electrical failures to physical defects. 

• Strong capability to read and understand Digital CMOS layouts, power grids, routing structures and SRAM arrays. 

• ATE test program debugging, and yield improvement experience. 

• Good interpersonal skills with the ability and desire to work as a standout colleague and problem solver. 

• Proven track record of working cross-functionally, learning fast, and driving issues to closure 

• Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release 

• Proficiency in programming languages: Python, C/C++, Perl for large-scale data analysis 

Preferred Skills 

• Develop fault isolation techniques using OBIRCH/IREM/LADA optical techniques. 

• Experience with advanced test data analysis tools and machine learning techniques for yield optimization. 

• Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects). 

• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking. 

• Knowledge of chip defect profiles and mitigation strategies across manufacturing steps. 

Location 

• North America based. Sunnyvale, up to 20% travel may be needed. 

The base salary range for this position is $175,000 to $250,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.