ASIC Digital Designer (HSE-TS-IMS-2026-189-GRAE)

CERN designs, develops, and operates particle accelerators and experiments for scientific research to understand the fundamental laws of the universe. These activities may generate stray radiation due to the interaction between beams and matter. The radiation detectors installed close to the various beam lines and targets allow CERN to accurately monitor radiation levels. Within the HSE-TS-IMS Section at CERN, the team is responsible for the design and development of this specialised equipment, as well as its installation, commissioning, operation, and maintenance.

Radiation monitoring is essential to enable CERN to operate its accelerator complex and related experiments while fulfilling its legal obligations to protect the public, people working on the CERN site, and the environment. In this stringent context, the TS-IMS Section is developing a new generation of ASICs to interface ionisation chamber signals with safety-critical monitoring systems, meeting challenging performance and reliability requirements.

Your responsibilities

You will work among a team of engineers and technicians to:

• Design, simulate, and verify the digital architecture of the next-generation ASIC front-end.
• Prepare RTL designs for tapeout using open-source EDA flows, including floorplanning and physical design preparation.
• Support post-fabrication bring-up, system characterisation, and functional/performance validation.
• Collaborate closely with analogue, verification, and SoC integration teams to ensure seamless system-level compatibility.

Your profile

• Hands-on experience with open-source ASIC EDA flows (Yosys, OpenROAD, LibreLane, etc.) from RTL to GDSII.
• Experience with floorplanning, constraint definition, and physical design preparation for tapeout.
• Post-tapeout prototype bring-up and hardware debugging experience is advantageous.
• Active contributions to open-source hardware projects or EDA toolchains are advantageous.
• Experience developing SoC submodules is advantageous.

Skills

• HDL design and simulation in VHDL, Verilog, or SystemVerilog.
• Good team player: collaboration skills across analogue, digital, verification, and SoC teams.
• Proficiency in Git, CI/CD pipelines, and automated verification workflows.
• Knowledge of RISC-V architecture.
• Familiarity with mixed-signal integration and digital interface protocols.
• Comfort with Linux-based development environments and scripting for automation (Python, Bash, etc.).
• Spoken and written English, with a commitment to learn French.

Eligibility criteria:

• You are a national of a CERN Member or Associate Member State.
• By the application deadline, you have a maximum of two years of professional experience since graduation in Electronics (or a related field) and your highest educational qualification is either a Bachelor's or Master's degree.
• You have never had a CERN fellow or graduate contract before.
• Applicants without University degree are not eligible.
• Applicants with a PhD are not eligible.