Sr Staff Design Verification Engineer

We are seeking a highly motivated and experienced SoC Design Verification Engineer to join our team. In this role, you will lead and contribute to the verification of complex System-on-Chip (SoC) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills.
Key Responsibilities
- Verification Planning: Develop and implement verification plans aligned with SoC specifications.
- Testbench Development: Design scalable, reusable testbenches using SystemVerilog and UVM.
- Debugging and Analysis: Identify and resolve design and verification issues.
- Coverage and Quality Assurance: Drive functional and code coverage to meet project goals.
- Leadership: Mentor junior engineers and lead verification for IP blocks or subsystems.
- Automation: Utilize scripting languages (Python, Perl, Tcl) to enhance verification efficiency.Technical Expertise:
- Proven experience in SoC design verification, including unit and combine test strategies.
- Strong knowledge of AMBA protocols: AHB, APB, AXI (mandatory) and IPs
- Proficiency in verification methodologies such as SystemVerilog, UVM (preferred), and SVA.
- Basic understanding of formal verification techniques and scripting using TCL, Python.
- Familiarity with programming languages like Verilog, assembly, C/C++.
- Knowledge of Functional Safety standards (e.g., ISO 26262) is a plus.