Senior Digital Verification Engineer

We are seeking an experienced Senior Digital Verification Engineer to lead end‑to‑end verification of complex IC blocks and systems.

Key Responsibilities

• Define Strategy & Ownership: Architect and execute comprehensive verification strategies, test plans, and  implement UVM-based environments from scratch.
• Verification Closure: Drive functional and code coverage to closure, utilizing constrained-random testing, assertion-based verification (SVA), and formal methods to prove design correctness.
• Specification Quality: Review design specifications early in the cycle to improve their quality, clarity, and "fitness for verification."
• Cross-Functional Collaboration: Partner with global architecture, design, and software teams to optimize hardware/software partitioning and system-level verification.
• Technical Leadership: Mentor and tutor junior engineers, champion design/verification reviews, and optimize automation flows for reusability and performance.
• Make/Buy Decisions: Participate in evaluating third-party VIP and tools, steering make/buy choices to ensure maximum engineering efficiency.