Sr Staff Engineer, Synthesis and STA

We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis. You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.  

Key Responsibilities 

• Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains. 
• Timing Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.  
• Constraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF). 
• Low-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains 
• Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies