Staff Engineer, ASIC Development Engineering (RTL Design)

In this role you will develop RTL for IPs and own it. Dealing the best of class IPs for all Sandisk products .

• hands on experience in IP / blocks / subsystem complex design in verilog / system verilog
• Strong digital design development and execution skills , solving bugs
• Deep experience in debug , solving problem, see the architecture view, proposing solutions.
• Working with EDA tools , CDC, RDC, Synthesis experience
• Deep knowledge on PCIe,  axi , DMA, AHB interfaces 
• Experience in coverage closure