Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)

Position Overview:

We are seeking a highly skilled and experienced Senior Engineer for our PNR function. The successful candidate will be part to a team of talented engineers responsible for ensuring the PNR convergence of our complex semiconductor designs. This role requires a deep understanding of PNR methodologies, leadership skills, and a strategic vision to drive continuous improvement in our PNR processes.

Key Responsibilities:

- Subsystem/block level ownership of Floorplanning, place and route flow for low power, high performance designs, debug of timing/power/area issues, clock tree analysis and assisting full chip timing convergence and timing closure.
- Collaborate with cross-function teams, including design, DFT to streamline PNR process

- Drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.
- Conduct thorough design and timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design convergence.

- Stay abreast of industry trends and emerging technologies in PNR and related fields, and incorporate best practices into the team’s workflow.

- Prepare and present detailed analysis, reports and technical documentation to stakeholders

- Foster a culture of innovation, collaboration, and continuous improvement within the PNR team.