Test Chip Designer

Design Engineer 

Standard Cell & Memory Compiler Characterization Silicon 

About the Role 

Silvaco/Mixel is seeking a Test Chip Designer to lead the end-to-end design, fabrication, and silicon validation of test vehicles used to characterize and qualify our standard cell libraries and memory compilers. In this role, you will own the test chip from architecture through tapeout, bring-up, and final silicon report — partnering closely with library development, memory compiler, characterization, and product engineering teams. Your test chips will directly determine the quality, accuracy, and competitive positioning of the IP we deliver to leading semiconductor customers worldwide. 

This is a high-impact, full-lifecycle hardware role for an engineer who enjoys both architecting silicon experiments. If you have built test chips for foundation IP and want to see your work shape the silicon strategy of a fast-growing EDA and IP company, we want to talk to you. 

Key Responsibilities 

Test Chip Architecture & Design 

• Define the overall test chip architecture, floorplan, and silicon experiment plan to fully characterize standard cell libraries and/or memory compilers across PVT corners, aging effects, and process variation. 
• Select and design appropriate on-chip test structures, including ring oscillators, FO1/FO4 delay chains, path-delay monitors, leakage and IDDQ structures, SRAM BIST/MBIST blocks, shmoo-capable bitcell arrays, and process monitors. 
• Specify coverage of cell types, drive strengths, threshold flavors, memory configurations, and corner cases needed to validate library timing, power, noise, and yield models. 
• Develop test chip specifications, block diagrams, pin lists, and interface protocols (scan, JTAG, I2C/SPI, parallel I/O) for ATE and bench measurement. 

Implementation, Place & Route 

• Own the full physical implementation of the test chip: synthesis, floorplanning, power planning, place and route, clock tree synthesis, and timing/DRC/LVS/ERC closure. 
• Drive integration of standard cells, memory instances, IO ring, ESD, PLLs, and any analog support blocks; resolve cross-functional issues with library, memory, and IO teams. 
• Run signoff flows including STA, parasitic extraction, EM/IR, antenna, DFM, and physical verification, working with foundry PDKs across advanced and mainstream nodes. 
• Prepare GDSII and all tapeout deliverables; lead tapeout reviews and interface with the foundry through mask release. 

Test Development & Silicon Bring-Up 

• Develop the complete test program for the chip on ATE platforms (e.g., Advantest, Teradyne) and on bench setups, including patterns, loadboards, and characterization scripts. 
• Define and implement DFT strategy: scan insertion, MBIST, boundary scan, on-chip clocking and observability hooks needed to extract meaningful silicon data. 
• Lead first silicon bring-up in the lab — debug, validate functionality, and establish a stable measurement environment for full characterization. 
• Manage the broader test campaign across temperature, voltage, and process splits; coordinate with product engineering, lab technicians, and external test houses. 

Data Analysis & Silicon Report 

• Analyze silicon measurements against pre-silicon models; correlate timing, power, leakage, Vmin/Vmax, and yield data with library and memory compiler models. 
• Identify model-to-silicon discrepancies and drive root-cause analysis with characterization, modeling, and library teams. 
• Author the formal silicon report documenting methodology, measurement results, correlation, and recommendations for model updates or library/compiler improvements. 
• Present findings to internal stakeholders and, where appropriate, to foundry partners and customers. 

Project & Stakeholder Management 

• Own the test chip schedule, budget, and risk register from concept through post-silicon report. 
• Coordinate across design, CAD, library, memory, project management, and foundry teams to keep the program on track. 
• Mentor junior engineers and contribute to building Silvaco’s broader test chip methodology and reusable IP.