Memory Senior Layout Engineer
Full-time Not ApplicableJob Overview
Technical Execution & Innovation
Own the layout design and verification of critical memory IP blocks, including floorplanning, placement, routing, and signoff.
Develop custom layouts from schematics, including leaf-cell layout and re-floorplanning for compiler porting, optimizing area under tight constraints.
Optimize floorplan, routing, and power distribution to reduce parasitic and IR drop; perform EMIR analysis to resolve electromigration and IR-drop issues to clean sign-off.
Execute the full physical-verification flow (DRC, LVS, ERC/VERC, antenna, ResCheck/CapCheck, DFM) and resolve complex multi-level violations under tight schedules.
Implement and update ECOs for device and connectivity changes, and drive them through to clean re-verification.
Troubleshoot and resolve layout issues, driving technical solutions and improvements.
Own the physical implementation of a complete memory instance or compiler sub-family, including its floorplan strategy, quality criteria, and release.
Quality, Automation & Methodology
Develop and implement automation scripts (Perl/Python/TCL/Shell/SKILL) to accelerate layout cycles and improve quality.
Follow and contribute to the design checklists, review gates, and sign-off criteria used by the Memory team, and generate the required documentation for release.
Conduct technical reviews and benchmarking of layout deliverables.
Introduce and implement methodology improvements that enhance layout quality and overall team efficiency.
Collaboration & Support
Work in close cooperation with Memory Design, Modeling, DFT, Physical Design, and CAD teams to deliver on time and according to required specifications.
Provide technical input on project planning and risk assessment, and collaborate with layout leads, CAD, and process teams to optimize layout flows and methodologies.
Contribute to the validation and debugging of fabricated silicon.
Provide mentorship and technical guidance to junior layout engineers and interns.