Memory Senior Circuit Engineer

Circuit Design & Implementation 

• Design and own memory circuit blocks at transistor level — row/column decoders, wordline drivers, pre-charge, sense amplifiers, write drivers, self-timed replica/tracking paths, control logic, level shifters, and IO — to the performance, power, and area targets defined in the specification. 

• Support instance and compiler development: implement and update designs so they remain correct and margin-clean across the configuration range of the compiler. 

• Execute ECOs and design changes for device sizing, connectivity, and margin fixes, and drive them through to clean re-verification. 

• Own a complete memory instance or compiler sub-family end to end, including its architecture choices, margin strategy, and PPA trade-offs. 

Simulation & Verification 

• Run pre- and post-layout SPICE simulation across all required PVT corners; verify function, timing, power, and leakage against specification. 

• Perform margin and statistical analysis — Monte-Carlo, bitcell read/write/hold margin, sense-amplifier offset, VMIN and retention analysis — and document the results for design review. 

• Close post-layout issues with the Layout team: parasitic impact, EMIR violations, coupling, and power-integrity findings. 

• Debug design mismatches and drive root-cause analysis together with the Modeling, Layout, and CAD teams. 

• Define the verification and corner strategy for the blocks under ownership, and review the simulation work of other engineers. 

Automation & Methodology 

• Develop scripts and automation (Perl/Python/TCL/Shell/SKILL) to accelerate simulation, data collection, and regression tasks, and integrate them within the memory compiler / view-generation environment. 

• Follow and contribute to the design checklists, review gates, and sign-off criteria used by the Memory team. 

• Introduce and implement methodology improvements that enhance design quality and overall team efficiency. 

Collaboration & Support 

• Work in close cooperation with Memory Layout, Modeling, DFT, Physical Design, and STA teams to deliver on time and according to required specifications, and escalate technical risks early. 

• Generate the required documentation, support characterisation and silicon correlation, and contribute to the validation and debugging of fabricated silicon. 

• Participate actively in design reviews — present your own work, and give and receive technical feedback constructively. 

• Provide mentorship and technical guidance to junior circuit engineers and interns.