Industry Product Specialist（Semiconductor Packaging Technology）

Key Responsibilities

Product Direction Guidance
• Advise on packaging module feature design and technical deconstruction depth based on advanced packaging technology evolution (e.g., CoWoS, HBM stacking, Chiplet interconnect, panel-level packaging)
• Identify high-value technical deconstruction scenarios (e.g., TSV process parameters → reliability correlation, Hybrid Bonding interface defects → yield impact pathways)
Technical Deconstruction & Knowledge Graph Construction
• Design packaging technology deconstruction frameworks (e.g., Packaging Architecture → Interconnect Technology → Process Steps → Equipment/Materials → Reliability Testing → Application Scenarios)
• Develop annotation schemas for extracting packaging process information from patents/literature (e.g., bonding temperature/pressure/surface activation processes, TSV aspect ratio/fill materials/electrical performance, thermal management solutions)
• Guide knowledge graph construction covering the process-equipment-material-performance-failure relationship network
Data Quality & Evaluation System
• Establish data annotation quality standards for the packaging domain, with emphasis on auditing accuracy of process parameters, technology roadmaps, and performance comparisons
• Design evaluation systems for platform packaging technical reports (process deconstruction granularity, technology roadmap completeness, competitive analysis depth)
• Conduct expert-level validation and feedback on platform-generated packaging technology insights
Industry Benchmarking & Resources
• Benchmark against advanced packaging technology roadmaps from TSMC, Intel, Samsung, and other industry leaders to ensure platform deconstruction logic aligns with industry practice
• Assist in building technology evolution timelines and milestone event libraries for the packaging domain

Requirements

 Education: Master’s degree or above in Microelectronics, Electronic Engineering, Materials Science, or related fields

Industry Experience: 5+ years in semiconductor packaging R&D, Process Integration (PIE), or advanced packaging technology development, with hands-on involvement in R&D or mass production ramp of at least one technology: 2.5D/3D packaging, TSV, or Hybrid Bonding

Technical Depth:

• • Familiar with advanced packaging process flows: RDL, Bump, TSV formation/filling, wafer thinning, bonding (thermocompression/hybrid bonding), molding, etc.
  • Understanding of packaging reliability testing standards (JEDEC, AEC, etc.) and failure analysis methodologies
  • Capable of extracting process innovation points and parameter optimization pathways from patents/technical literature 
  •  Understanding of interconnect challenges and solutions in Chiplet architecture
  Product Mindset: Ability to translate complex packaging process knowledge into structured data requirements and evaluation standards 
   
  Preferred: R&D/process engineering background at leading packaging companies (TSMC, Intel, Samsung, ASE, Amkor); experience with HBM, CoWoS, or similar high-volume production